#ALTERA DSP BUILDER CODE#
The HDL Import block allows you to import either HDL code (VHDL or Verilog HDL) or an entire Quartus II project into your DSP Builder design. Using the AltBus block in this mode is described in more detail in Generic Simulink Blocksets on page 11. The explicit black-box interface consists of the AltBus block in the Black Box Input Output mode.
Using these blocks prevents SignalCompiler from translating the sub-element of the design into HDL code.įor more information on using the SubSystemBuilder block, refer to SubSystemBuilder Block on page 6. Non-DSP Builder blocksets include generic Simulink blocksets and HDL designs imported using the SubSystemBuilder block. You instantiate the explicit black-box interface to integrate non-DSP Builder blocksets into your DSP Builder design. This block is described in more detail in HDL Import Block. SignalCompiler recognizes the HDL Import block as a black box and bypasses it during the HDL translation. When you instantiate the HDL Import block, it automatically indicates the subsystem underneath is a black box. The implicit black-box interface can be inferred by the HDL Import block. There are two types of black-box interfaces in DSP Builder: implicit and explicit. Improving efficiency by allowing you to reuse existing HDL modules Providing an integrated design environment allowing co-simulation of existing HDL modules, pre-compiled Quartus II projects, and generic Simulink blocksets The benefits of using black boxes in the design flow include: SignalCompiler achieves this by using the black-box interface. The black-box interface can also be used to encapsulate non-DSP Builder blocksets such as generic Simulink blocksets.īlack-Boxing Black-boxing allows SignalCompiler in DSP Builder to recognize subsystems that should not be altered during the conversion process from Simulink to HDL. When evaluating a design at the system level, you may want to integrate generic Simulink blocksets into your DSP Builder design. DSP Builder also generates the simulation model automatically that allows the co-simulation of these HDL subsystems within the Simulink environment. The DSP Builder design flow supports integrating HDL code or pre-compiled Quartus II projects with DSP Builder blocks.
Rather than recoding these blocks using DSP Builder blocksets, it is more efficient to import them directly into the system. In other cases, there may be existing HDL code (either Verilog HDL or VHDL) that needs to be integrated into the overall DSP Builder design. Non-DSP Builder subsystems may be control logic or complex state machines that are more suited for HDL coding than DSP Builder blocksets. Using black boxes allows you to bridge the boundaries or partitions between the DSP Builder subsystems and the non-DSP Builder subsystems. Introduction When using DSP Builder to design a system, you may need to integrate some modules or subsystems that were created using non-DSP Builder blocksets into the system. Altera Corporation 1AN-402-1.0 Preliminary
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